Contactar Jorge Filipe Leal Costa Semião

Jorge Semiao

Unidade Orgânica:

ISE

Categoria:

Professor Adjunto

Subsistema:

Politécnico

Outro centro de investigação:

INESC-ID

Regime:

Exclusividade

Vínculo:

CT em Funções Públicas por tempo indeterminado

O Professor Jorge Semião é Doutorado, Mestre e Licenciado em Engenharia Electrotécnica e de Computadores pelo Instituto Superior Técnico da Universidade Técnica de Lisboa, com especialização na área de Microelectrónica e Sistemas Electrónicos e Computadores. Começou a trabalhar em investigação no INESC (Instituto de Engenharia de Sistemas e Computadores) em 1995 e, desde então é investigador no INESC-ID em Lisboa (Instituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa), trabalhando no grupo “Quality, Test and Co-Design of HW/SW Systems”. As suas principais áreas de investigação e competências são o projecto e optimização de circuitos integrados digitais, o projecto para testabilidade e o teste de circuitos electrónicos, o projecto de circuitos tolerantes a falhas e o envelhecimento dos circuitos electrónicos. Participou em diversos projectos de investigação (12), e é autor e co-autor de mais de uma centena de artigos científicos publicados, cinco patentes nacionais e mais quatro patentes ainda sob processo de registo. Obteve ainda prémios para “Melhor aluno de Doutoramento do INESC-ID em 2010”, de “Melhor Estágio em Engenharia Electrotécnica” (atribuído pela Ordem dos Engenheiros, em 2001), e de “Melhor Professor do Curso de Licenciatura em Engenharia Eléctrica e Electrónica” (EST - Universidade do Algarve, em 1999). Relativamente à docência no ensino superior, leccionou como bolseiro no IST em 1996/97 e desde 1997 até ao momento é Professor no Instituto Superior de Engenharia da Universidade do Algarve, actualmente na categoria de Professor Adjunto, tendo leccionado diversas disciplinas nas áreas de Electrónica e de Electricidade.

Habilitações Literárias
- Doutoramento em Engenharia Electrotécnica e de Computadores, pelo Instituto Superior Técnico - UTL
- Mestrado em Engenharia Electrotécnica e de Computadores, pelo Instituto Superior Técnico - UTL
- Licenciatura em Engenharia Electrotécnica e de Computadores, pelo Instituto Superior Técnico - UTL

Carreira Profissional
Investigação:
- Investigador sénior no INESC-ID Lisboa (Instituto de Eng. e Sistemas de Computadores - Investigação e Desenvolvimento em Lisboa) (2000 - presente)
- Investigador colaborador do CEOT (Centro de Electrónica, Optoelectrónica e Telecomunicações) na UAlg (2010 - 2012)
- Estagiário no INESC (1995 - 1999)
Docência:
- Docente no Instituto Superior de Engenharia (antiga Escola Superior de Tecnologia) - UAlg (1997 - presente)
- Docente no IST como bolseiro de Mestrado (1996 - 1997)
- Formador de Informática no IPFEL (1996 - 1997)

Prémios
3- Prémio para "Melhor aluno de Doutoramento do INESC-ID", 2010.
2- Prémio para “Melhor Estágio” em Engenharia Electrotécnica atribuído pela Ordem dos Engenheiros no ano de 2001, com um estágio realizado no INESC sobre o tema: “Técnicas de Introdução de DFT a Nível de Sistema em Sistemas Físicos e Lógicos (Hw/Sw)”.
1- Homenageado pelo Núcleo Pedagógico da Escola Superior de Tecnologia da Universidade do Algarve, pelo trabalho de docência realizado na EST-UAlg, e por ter sido reconhecido pelos alunos como um dos melhores professores do curso de Engª Eléctrica e Electrónica, em 27 de Novembro de 1999.

Detalhes

Projetos

Research & Development Projects
20- Project RETINA: "infRaestrutura para caractErização de douradas para Treino de algorItmos de iNteligência Artificial", prestação de serviço de investigação e desenvolvimento financiado pela ALTICE LABS [dezembro 2020 - Julho 2022].
19- Project INSPECT: "non-INtruSive Performance monitoring for EleCtric sysTems" (Monitorização Não-Intrusiva da Performance em Sistemas Eléctricos), Sistema de Incentivos à Investigação e Desenvolvimento Tecnológico (SI I&DT), AVISO Nº 17/SI/2019, Projecto em Copromoção com a empresa FULGUR IT, Portugal 2020, CRESC2020, FEDER [Dezembro 2020 - Junho 2023]
18- Project WELSAFE.DV: "Welcome Safety Device", AAC 15/SI/2020, Sistema de Incentivos Atividades de Investigação e Desenvolvimento e Investimento em Infraestruturas de Ensaio e Otimização (Upscaling) no contexto do Covid-19, I&D Empresas - Covid-19, em co-promoção, Portugal2020, CRESC2020, FEDER. [Jun. 2020 – Fev. 2021]
17- Project KCITAR Algarve, financiado através do Fundo Social Europeu no Eixo Prioritário 8 - Modernizar e Capacitar a Administração, do Programa Operacional Regional do Algarve. [2019 - Dezembro de 2021].
16- Project TTUES: "Sustainable Electric Urban Touristic Transportation" (translated from "Transporte Turístico Urbano Eléctrico Sostenible"), project ID 0517_TTUES_6_E, financed by the European Union, in the aim of the POCTEP program, by the European Regional Development Fund (ERDF), from Nov. 2019 until Dec. 2021.
15- Project KTTSEADRONES: “Conocimiento y transferencia de tecnología sobre vehículos aéreos y acuáticos para el desarrollo transfronterizo de ciencias marinas y pesqueras", Refª: 0622_KTTSEADRONES_5_E, financed by Programa de Cooperação Interreg V A España - Portugal (POCTEP) 2014-2020, from June 2019 until December 2021, budget UAlg: 256742,49€.
14- Project PROTeuS: PROmoting security and safeTy by crEating a MED cluster on Maritime Surveilance, nº 137, INTERREG Mediterranean program, projet coordinator: Chamber of Commerce, Industry, Crafts and Agriculture of Venice Rovigo Delta – Lagunare (Veneza, Itália); UAlg (participant). [Nov. 2016 – Out. 2019 (participation from Jan.2019 - Out.2019)] (UAlg: 258.218 €)
13- Polo Tecnológico do Algarve, ALG-01-0246-FEDER-000001, ALGARVE 2020 (2018 a 2020) 12- Project "AGERAR: Almacenamiento y gestión de energías renovables en aplicaciones comerciales y residenciales", financed by INTERREG V-A España – Portugal (POCTEP), from July 2017 to September 2019.
11- Project "M5SAR: Mobile Five Senses Augmented Reality System for Museums", financed by Portugal2020, CRESC Algarve 2020 I&DT, nº 3322, promotor SPIC - Sonha Pensa Imagina Comunica, Lda., co-promotor UAlg (2016 – 2018).
10- Project "i3FR: Intelligent Fresh Food Fleet Router", funded by QREN I&DT, n.º 34130, promotor X4DEV - Business Solutions, SA, co-promotor Universidade do Algarve, from 2013 to 2015.
9- Project "Managing The Inteligence - MTI", QREN Project nº 2013/030260, a cooperation between Univ. of Algarve and Certigarve company, from 2013 to 2015.
8- Project MEDIAN (ManufacturablE and Dependable multIcore Architectures at Nanoscale), a COST Action (IC1103) aimed at creating an European network of competence and experts on all dependability aspects of future digital systems development, promoting collaboration between industry and research (2012-2015).
7- Project ENIAC SE2A WP3.2.3d/e (IE04015) - Eniac SE2A (01-Jan-2009 to 01-Dec-2011), carried out at INESC-ID Lisbon, financed by EC/FCT, partnerships: Amepox (Company) -Poland, BME; Ltd (Company) -Hungary, Boschman (Company) -Netherlands, Forth IESL - Institute of Electronics Structure and Laser (Other) -Greece, IMEL - Institute of Microelectronics (Other) -Greece, IMT - National Institute for Research and Development in Microtechnologies (Other) - Bucharest, Romania, INESC MN (Other) - Lisbon, Portugal, INESC-ID (Other), INOV (Other), ITE - Institute of Electron Technology (Other) - Warsaw, Poland, M2I - Material Innovation Institute (Company) -Netherlands, MFA - Research Institute for Technical Physics and Material Science (Other) -Hungary, NXP Semiconductors (Company) - Eindhoven, The Netherlands, OPTRONIC (Company) - Stockholm, Sweden, SP - Technical Research Institute of Sweden (Other) -Sweden, Theta Microelectronics (Company) -Greece, TNO (Company) -Netherlands, University of Technology and Economics of Budapest (University) -Hungary, VTEC - Volvo (Company) -Sweden, WESZTA; Ltd (Company) -Hungary, WRUT- Wroclaw University of Technology (University) - Wroclaw, Poland.
6- Project POSC/EEA-ESE/57405/2004 (2005-2008), sponsored by FCT, entitled to : “Nano SoC Dynamic Test (Teste Dinâmico de Sistemas Integrados em Nanotecnologias)”, carried out at INESC-ID, in a partnership with University of Algarve and "Instituto Superior Técnico".
5- Project POCTI/FP/FNU/50131/2003, sponsored by FCT, entitled to : “Colaboration in the CMS Experiment”, carried out at "Laboratório de Instrumentação e Física Experimental de Partículas - LIP – Lisboa" in a partnership with INESC-ID, from 2004/07/04 to 2005/09/30.
4- Project POCTI/FNU/49481/2002, sponsored by FCT, entitled to : “Colaboration in the CMS Experiment”, carried out at "Laboratório de Instrumentação e Física Experimental de Partículas - LIP – Lisboa" in a partnership with INESC-ID, from 2003/03/21 to 2004/07/31.
3- CERN/P/FIS/15170/1999, entitled to “Collaboration in the CMS Experiment”, carried out at "Laboratório de Instrumentação e Física Experimental de Partículas - LIP – Lisboa" in partnership with INESC-ID and TECMIC.
2- Project CERN/P/FAE/1147/97 (1998-2000), sponsored under the PRAXIS XXI Program, entitled to: “A R&D Project of Collaboration with CERN in the CMS Experiment”, carried out ay INESC-id, in a partnership with CERN and LIP, from Lisbon.
1- Project ICCTI/CAPES (nº 423/CAPES) (1997-2000), under the convenant ICCTI (Portugal) / CAPES (Brasil), entitled to: “Especificação, projecto e Teste de Sistemas Electrónicos Confiáveis, com Ênfase na Prototipação Rápida para Aplicações de Tempo Real”, realizado no IST/INESC, de Lisboa, em colaboration with Federal University of Rio Grande do Sul (UFRGS) (Porto Alegre, Brazil) and Engineering Faculty from University of Porto (FEUP). This project was sponsored by "Instituto para a Cooperação Científica e Tecnológica Internacional (ICCTI)" and by "Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES, Brasil)".

Publicações

Patents
10- Portuguese Patent Pending - entitled to "Performance Sensor for CMOS Memory Cells“ (Sensor de Performance para Células de Memória CMOS), October 2020.
9- Portuguese Patent Pending - PT 110840, entitled to "Non-intrusive Performance Sensor for Reliable Subthreshold Voltage Operation" (Sensor De Desempenho Não Intrusivo Para Operação Confiável De Circuitos Digitais), July 12, 2018.
8- Portuguese Patent Pending - entitled to "Portable Device for Touch, Taste and Smell Sensations in Augmented Reality Experiences", 2017.
7- Portuguese Patent Pending - entitled to "Performance Sensor for Subthreshold Voltage Operation", 2017.
6- Portuguese Patent – PT 108852, entitled to "Performance and Aging Sensor for SRAM and DRAM Memories", requested by University of Algarve, in September 29, 2015, from: J. Semião, H. Santos, A. Romão, approved in September 18, 2017.
5- Portuguese Patent – PT 107979, entitled to "Mecanismo Distribuído de Escalonamento de Cargas Elétricas para Micro-Redes", requested by University of Algarve, in October 21, 2014, from: J. Monteiro, P. Cardoso, J. Eduardo, J. Semião, approved in March 30, 2020.
4- Portuguese Patent – PT 107887, entitled to "Flip-Flop Tolerante a Erros de Performance com Sinalização de Transições Críticas", requested by University of Algarve, in September 16, 2014, from: J. Semião, J. P. Teixeira, I. C. Teixeira, A. Romão, D. Saraiva, approved in April 10, 2019.
3- Portuguese Patent – PT 106513, entitled to "Optimização ao Longo da Vida da Dissipação de Potência ou da Performance em Circuitos Integrados Digitais Síncronos", requested by University of Algarve, in August 29, 2012, from: J. Semião, I. C. Teixeira, J. P. Teixeira, A. Romão, approved in May 28, 2014.
2- Portuguese Patent – PT 105636, entitled to "Flip-Flop com Sensor para Previsão de Erros de Performance, para Aplicação como Sensor Local de Performance ou de Envelhecimento em Circuitos Integrados Digitais Síncronos", requested by University of Algarve, in April 20, 2011, from: C. V. Martins, J. Semião, I. C. Teixeira, J. P. Teixeira, approved in May 17, 2013.
1- Portuguese Patent – PT 103436, entitled to “Aumento de Tolerância Dinâmica de Circuitos Electrónicos Integrados Digitais a Variações de Tensão de Alimentação e de Temperatura”, in February 17, 2006, requested by INESC-ID, University of Vigo – CACTI and PUCRS (Catholic University of Rio Grande do Sul), from: João Paulo Cacho Teixeira, Isabel Cacho Teixeira, Marcelino Bicho dos Santos, Jorge Filipe Leal Costa Semião, Juan Rodriguez Andina, Marcial Irago, Fabian Vargas and Leonardo Piccoli.

Books' Editor
2- "Harnessing the Internet of Everything (IoE) for Accelerated Innovation Opportunities", Editors: Pedro J.S. Cardoso, Jânio Monteiro, Jorge Semião, João M.F. Rodrigues, IGI Global, February, 2019, ISBN13: 9781522573326, ISBN10: 1522573321, EISBN13: 9781522573333, DOI: 10.4018/978-1-5225-7332-6.
1- INCREaSE, Proceedings of the 1st International Congress on Engineering and Sustainability in the XXI Century - INCREaSE 2017, Editors: A. Mortal, J. Aníbal, J. Monteiro, C. Sequeira, J. Semião, M. Moreira da Silva, M. Oliveira, Springer, 2018, DOI: https://doi.org/10.1007/978-3-319-70272-8.

Publications
107- Jorge Semiao, Luis Santos, Marcelino B. Santos, “DRAM Performance Sensor”, Proceedings of the 24th International Conference On Human-Computer Interaction, HCII 2022, 26 June - 1 July, DOI: https://doi.org/10.1007/978-3-031-05028-2_34.
106- Ricardo J.M. Veiga *, Jorge Semião *, João M.F. Rodrigues *, Luís Bentes, Iñigo Exposito Ochoa, João P. Silva, Adela Belackova, “Autonomous Temporal Pseudo Labeling For Fish Detection”, Journal of Applied Sciences, Section of Computing and Artificial Intelligence, Machine Learning in Computer Engineering Applications, June 2022, https://doi.org/10.3390/app12125910.
105- Salvador P. Litrán; Eladio Durán; Jorge Semião; Cristian Díaz-Martín, “Multiple-Output DC–DC Converters: Applications and Solutions”, Electronics, 2022-04-15, Journal article, MDPI, Special issue DC-DC multiple output, DOI: https://doi.org/10.3390/electronics11081258
104- Cardoso, P. J., Monteiro, J., Cabrita, C., Semião, J., Cruz, D. M., Pinto, N., ... & Rodrigues, J. M. (2022). Monitoring, Predicting, and Optimizing Energy Consumptions: A Goal Toward Global Sustainability. In Research Anthology on Smart Grid and Microgrid Development (pp. 1409-1437). IGI Global. DOI: https://doi.org/10.4018/978-1-6684-3666-0.ch064 (reprint)
103- Veiga, R., Semião, J. & Rodrigues, João M.F. (2021). An Initial Approach to Self-Supervised Underwater Fish Detection. In Procs of the 27th Portuguese Conference on Pattern Recognition, Evora, Portugal, pp. 59-60.
103- Jorge Semião, Luís Santos and Marcelino Santos, “SRAM Performance Sensor”, Proceedings of the Proceedings of the XXXVI edition of the Design of Circuits and Integrated Systems Conference (DCIS 2021), November 24-26th 2021, Vila do Conde, Portugal, DOI: https://doi.org/10.1109/DCIS53048.2021.9666163.
102- Pedro J.S. Cardoso, Cristiano Cabrita, Dario Cruz, Nelson Pinto, Jânio Monteiro, Jorge Semião, Célia Ramos, Luís Oliveira, João M.F Rodrigues, (2020). Monitoring, Prediction, and Optimization of Consumptions in Buildings: A Goal Toward Global Sustainability. Chapter 5 in Smart Systems Design, Applications and Challenges (pp. 80-107), IGI Global. DOI: 10.4018/978-1-7998-2112-0.ch005
101- SP Litrán, E Durán, J Semião, RS Barroso, "Single-switch bipolar output DC-DC converter for photovoltaic application", Electronics 9 (7), 1171, Published on July 18th, 2020, doi: https://doi.org/10.3390/electronics9071171
100- J. Semião, E. Durán, S. P. Litrán, M. B. Ferrera, "Multiple-Output Switched-Capacitor DC-DC Combination Converters for IoT Applications", Proceedings of IEEE 14th International Conference on Compatibility, Power Electronics and Power Engineering (CPE-POWERENG), 8-10 July 2020, Setubal, Portugal, DOI: 10.1109/CPE-POWERENG48600.2020.9161680
99- S. P. Litrán, E. Durán, R. S. Barroso, J. Semião, M. B. Ferrera, "Analysis of Converters with Bipolar Output for DC Microgrid", Proceedings of IEEE 14th International Conference on Compatibility, Power Electronics and Power Engineering (CPE-POWERENG), 8-10 July 2020, Setubal, Portugal, DOI: 10.1109/CPE-POWERENG48600.2020.9161664.
98- J. Semião, M. B. Santos, I. C. Teixeira, J. P. Teixeira, "Internet of Things and Artificial Intelligence - A Wining Partnership?", Boo chapter from Convergence of Artificial Intelligence and the Internet of Things, pp 369-390, Part of the Internet of Things book series (ITTCC), First Online: 07 May 2020, DOI: https://doi.org/10.1007/978-3-030-44907-0_15.
97- Salvador P. Litrán, Eladio Durán, M. Bella Ferrera, Jorge Semião, Rafael S. Barroso, "A Zeta-CSC Converter Combination for Single-Input and Bipolar Output", Proceedings of the IECON 2019 - 45th Annual Conference of the IEEE Industrial Electronics Society, Lisbon Congress Center, Lisbon, Portugal, 14-17 October, 2019: DOI: https://doi.org/10.1109/IECON.2019.8927458.
96- J. Semião, H. Santos, R. Cabral, M. B. Santos and P. Teixeira, "PVTA-Aware Performance SRAM Sensor for IoT Applications", Proceedings of the 2nd INternational CongRess on Engineering and Sustainability in the XXI cEntury – INCREaSE 2019, Springer, Pages 337-353, October 09-11, 2019, DOI: https://doi.org/10.1007/978-3-030-30938-1.
95- Jorge Semião, Ruben Cabral, Hugo Cavalaria, Marcelino Santos, Isabel C. Teixeira, J. Paulo Teixeira, "Ultra-Low-Power Strategy for Reliable IoE Nanoscale Integrated Circuits", book chopter in "Harnessing the Internet of Everything (IoE) for Accelerated Innovation Opportunities", IGI Global, February, 2019, DOI: https://doi.org/10.4018/978-1-5225-7332-6.ch011.
94- Nelson Pinto, Dario Cruz, Jânio Monteiro, Cristiano Cabrita, Jorge Semião, Pedro J. S. Cardoso, Luís M. R. Oliveira, João M. F. Rodrigues, "IoE-Based Control and Monitoring of Electrical Grids: A Smart Grid's Perspective", pages 57-82, book chapter in "Harnessing the Internet of Everything (IoE) for Accelerated Innovation Opportunities", IGI Global, February, 2019, DOI: https://doi.org/10.4018/978-1-5225-7332-6.ch003.
93- J. Semião, R. Cabral, M. Santos, I. Teixeira, P. Teixeira, "Performance Sensor for Reliable Operation", Accepted for publication at UAHCI: 12th International Conference on Universal Access in Human-Computer Interaction, integrated in the 20th HCII, Las Vegas, USA, July, 2018, DOI: https://doi.org/10.1007/978-3-319-92052-8_28.
92- J. Monteiro, D. Cruz, N. Pinto, P. Cardoso, C. Cabrita, J. Semião, L. Oliveira, J. Rodrigues, "Development of an Energy Management System for the Charge Scheduling of Plug-In Electric Vehicles", Accepted for publication at UAHCI: 12th International Conference on Universal Access in Human-Computer Interaction, integrated in the 20th HCII, Las Vegas, USA, July, 2018, DOI: https://doi.org/10.1007/978-3-319-92052-8_17.
91- J.D.P. Sardo, J.A.R. Pereira, R.J.M. Veiga, J. Semião, P.J.S. Cardoso, J.M.F. Rodrigues, "Multisensorial Portable Device for Augmented Reality Experiences in Museums", Accepted for publication at the 18th International Conference on Instrumentation, Measurement, Circuits and Systems, Paris, France, April, 2018. (link)
90- S. Nogin, J. Monteiro, S. Gómez-Melgar, J. Peyroteo, A. Mortal, C. M. Santos, J. Livramento, P. J. S. Cardoso, J. Semião, "A Platform for the Promotion of Energy Efficiency and Monitoring in Hotel Units", Chapter in "Handboof of Research on Technological Developments for Cultural Heritage and eTourism Applications", IGI Global, pages 420-448, 2018, DOI: https://dx.doi.org/10.4018/978-1-5225-2927-9.ch020.
89- J.M.F. Rodrigues, P.J.S. Cardoso, J. Lessa, J.A.R. Pereira, J.D.P. Sardo, M. Freitas, J. Semião, J. Monteiro, C.M.Q. Ramos, R. Lam, E. Esteves, M. Figueiredo, A. Gonçalves, M. Gomes, P. Bica, "An Initial Framework to Develop a Mobile 5 Sense Museum System", Chapter in "Handboof of Research on Technological Developments for Cultural Heritage and eTourism Applications", IGI Global, pages 96-119, 2018, DOI: https://dx.doi.org/10.4018/978-1-5225-2927-9.ch005.
88- Eladio Duran Aranda, María Bella Ferrera Prieto, Salvador Pérez Litrán, Antonio Javier Barragán Piña, Juan Manuel Enrique Gómez, José Manuel Andújar Márquez, Jorge Semião, Jânio Monteiro and Isménio Martins, "An application of Interleaved Zeta-Buck-Boost Combination Converter in Distributed Generation", Proceedings of the 1st INternational CongRess on Engineering and Sustainability in the XXI cEntury - INCREaSE 2017, Faro, Portugal, October 11-13, 2017, Edited by Springer, DOI: https://doi.org/10.1007/978-3-319-70272-8_25.
87- Juan Manuel Enrique Gómez, Antonio Javier Barragán Piña, Eladio Durán Aranda, Juan Ríos Gutiérrez, José Manuel Andújar Márquez, Isménio Martins, Jânio Monteiro and Jorge Semião, "Tracker based on Maximum-Power Point Resistance Modeling versus a classic P&O", Proceedings of the 1st INternational CongRess on Engineering and Sustainability in the XXI cEntury - INCREaSE 2017, Faro, Portugal, October 11-13, 2017, Edited by Springer, DOI: https://doi.org/10.1007/978-3-319-70272-8_35.
86- Jose Ignacio Otero Bueno, Juan Daniel Mozo Llamazares, Eladio Duran Aranda and Jorge Semião, "An Open Hardware Electronic Controller for Motorized Rotary Injection Valves Used in Flow Injection Analysis", Proceedings of the 1st INternational CongRess on Engineering and Sustainability in the XXI cEntury - INCREaSE 2017, Faro, Portugal, October 11-13, 2017, Edited by Springer, DOI: https://doi.org/10.1007/978-3-319-70272-8_22.
85- Hugo Cavalaria, Ruben Cabral, Jorge Semião, Marcelino Santos, Isabel Teixeira and Paulo Teixeira, "Power-Delay Analysis For Subthreshold Voltage Operation", Proceedings of the 1st INternational CongRess on Engineering and Sustainability in the XXI cEntury - INCREaSE 2017, Faro, Portugal, October 11-13, 2017, Edited by Springer, DOI: https://doi.org/10.1007/978-3-319-70272-8_30.
84- Ruben Cabral, Hugo Cavalaria, Jorge Semião, Marcelino Santos, Isabel Teixeira and Paulo Teixeira, "Performance Sensor For Subthreshold Voltage Operation", Proceedings of the 1st INternational CongRess on Engineering and Sustainability in the XXI cEntury - INCREaSE 2017, Faro, Portugal, October 11-13, 2017, Edited by Springer, DOI: https://doi.org/10.1007/978-3-319-70272-8_31.
83- Sergey Nogin, Jorge Semião and Jânio Monteiro, "A non-intrusive IoT system for the Detection of Faults in Internal Combustion Engines", Proceedings of the 1st INternational CongRess on Engineering and Sustainability in the XXI cEntury - INCREaSE 2017, Faro, Portugal, October 11-13, 2017, Edited by Springer, DOI: https://doi.org/10.1007/978-3-319-70272-8_28.
82- J. D. P. Sardo, J. Semião, J. M. Monteiro, E. Esteves, J. Pereira, M. Freitas and J. M. F. Rodrigues, "Portable Device for Touch, Taste and Smell Sensations in Augmented Reality Experiences", Proceedings of the 1st INternational CongRess on Engineering and Sustainability in the XXI cEntury - INCREaSE 2017, Faro, Portugal, October 11-13, 2017, Edited by Springer, DOI: https://doi.org/10.1007/978-3-319-70272-8_26.
81- J. Semião, H. Santos, R. Cabral, A. Romão, M. Santos, I.C. Teixeira, J.P. Teixeira, "Aging and Performance Sensor for SRAM", Proceedings of the XXXI edition of the Design of Circuits and Integrated Systems Conference (DCIS 2016), November, 23rd-25th, Granada (Spain), 2016, DOI: https://doi.org/10.1109/DCIS.2016.7845354.
80- Pedro J.S. Cardoso, Gabriela Schütz, Jorge Semião, Jânio Monteiro, João Rodrigues, Andriy Mazayev, Emanuel Ey, Micael Viegas, "Integration of a real-time stochastic routing optimization software with an enterprise resource planner", in "Geographical Information Systems Theory, Applications and Management", Volume 582, of the series "Communications in Computer and Information Science", pp 124-141, Springer International Publishing, January 26th, 2016, DOI: http://dx.doi.org/10.1007/978-3-319-29589-3_8.
79- C. Leong, J. Semião, M. B. Santos, I. C. Teixeira, J. P. Teixeira, "Fault-Tolerance in Field Programmable Gate Array with Dynamic Voltage and Frequency Scaling", Journal of Low Power Electronics (JOLPE), Volume 11, Number 4, pp. 517-527, December, 2015, DOI: https://doi.org/10.1166/jolpe.2015.1406.
78- J. Semião, R. Cabral, M. B. Santos, I. C. Teixeira, J. P. Teixeira, "Dynamic Voltage and Frequency Scaling for Long-Term and Fail-Safe Operation", The Finale Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN Finale'15), Tallinn, Estonia, November 10-11, 2015 (link).
77- C. Leong, J. Semião, M.B. Santos, I.C. Teixeira, J.P. Teixeira, A.J.N Batista, B. Gonçalves, J.G. Marques, "Fast Radiation Monitoring in FPGA-based Designs", Proceedings of the XXX Conference on Design of Circuits and Integrated Systems (DCIS'15), Estoril, Portugal - November 25-27, 2015, DOI: https://doi.org/10.1109/DCIS.2015.7388590.
76- Pedro J.S. Cardoso, Gabriela Schütz, Jorge Semião, Jânio Monteiro, João Rodrigues, Andriy Mazayev, Emanuel Ey, Micael Viegas, Carlos Neves, Sérgio Anastácio, "Integration of a food distribution routing optimization software with an enterprise resource planner", Proceedings of the 1st International Conference on Geographical Information Systems Theory, Applications and Management, Barcelona, Spain, 28-30 April, 2015, ISBN 978-989-758-099-4, pages 153-161, DOI: http://dx.doi.org/10.5220/0005385901530161.
75- C. Leong, J. Semião, M.B. Santos, I.C. Teixeira, J.P. Teixeira, "Fault-Tolerance in FPGA Focusing Power Reduction or Performance and Enhancement", Proceedings of the16TH IEEE Latin American Test Symposium (LATS2015), March 25-27, 2015, pages 1-6, DOI: http://dx.doi.org/10.1109/LATW.2015.7102523.
74- J. Semião, R. Cabral, C. Leong, M. B. Santos, I. C. Teixeira, J. P. Teixeira, "Dynamic Voltage Scaling with Fault-Tolerance for Lifetime Operation", The Fourth Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'15) / DATE’2015 Workshop W06, Grenoble, France, March 13, 2015 (link).
73- J. Semião, A. Romão, C. Leong, M. Santos, I. Teixeira, P. Teixeira, "Aging-Aware Dynamic Voltage or Frequency Scaling", Proceedings of the XXIX Conference on Design of Circuits and Integrated Systems (DCIS'14), Madrid, Spain, November 26-28, 2014, DOI: http://dx.doi.org/10.1109/DCIS.2014.7035599.
72- Jânio Monteiro, Jorge Eduardo, Pedro J.S. Cardoso, Jorge Semião, "A Distributed Load Scheduling Mechanism for Micro Grids", IEEE International Conference on Smart Grid Communications (IEEESmartGridComm), 3 - 6 November 2014, Venice, Italy, DOI: http://dx.doi.org/10.1109/SmartGridComm.2014.7007659.
71- L. Sousa, J.M.F. Rodrigues, J. Monteiro, P.J.S. Cardoso, J. Semião, R. Alves, "A 3D Gesture Recognition Interface for Energy Monitoring and Control Applications", Proc. 13th Int. Conf. on Applications of Computer Engineering (ACE '14), Lisbon, Portugal, Oct. 30-Nov. 1, 2014, pp. 62-71. ISBN: 978-960-474-393-3 (link).
70- J. Semião, A. Romão, D. Saraiva, C. Leong, M. Santos, I. Teixeira, P. Teixeira, "Performance Sensor for Tolerance and Predictive Detection of Delay-Faults", accepted for publication in the DFT (International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems) Symposium 2014, Amsterdam, The Netherlands, October 1-3, 2014, DOI: http://dx.doi.org/10.1109/DFT.2014.6962092.
69- A. Romão, J. Semião, C. Leong, M. B. Santos, I. C. Teixeira, J. P. Teixeira, "Power and Performance Optimization in Long-term Operation", The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'14), Dresden, Germany, March 28, 2014, (link).
68- J. Coelho, J. Semião, C. Leong, M. B. Santos, I. C. Teixeira, J. P. Teixeira, "Aging Monitoring Methodology for Built-In Self-Test Applications", The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'14), Dresden, Germany, March 28, 2014, (link).
67- C. Leong, J. Semião, M. Santos, I. Teixeira, P. Teixeira, "Production and Lifetime Performance Enhancement in FPGA Designs", 28th Conference on Design of Circuits and Integrated Systems (DCIS 2013), Donostia, San Sebastian, November 27-29, 2013 (link).
66- C. Leong, J. Semião, I. Teixeira, M. Santos, M. Valdés, J. Freijedo, J. Rodriguez, F. Vargas, J. Teixeira, "Aging Monitoring with Local Sensors in FPGA-based Designs", 23rd International Conference on Field Programmable Logic and Applications (FPL'13), Porto, Portugal, Sept. 2-4, 2013, DOI: http://dx.doi.org/10.1109/FPL.2013.6645596.
65- M.Valdés, M.J.Moure, J.J.Rodríguez-Andina, J.Freijedo, J.Semião, F.Vargas, I.C.Teixeira, J.P.Teixeira, "Design and validation of configurable on-line aging sensors in nanometer-scale FPGAs", IEEE Transactions on Nanotechnology, publicado primeiro on-line em 21 de Março, 2013, DOI: http://dx.doi.org/10.1109/TNANO.2013.2253795.
64- J.Vazquez, V. Champac, J.Semião, M. Santos, I.C.Teixeira, J.P.Teixeira, "Process Variations-aware Statistical Analysis Framework for Aging Sensors Insertion", Journal of Electronic Testing: Theory and Applications (JETTA), publicado primeiro on-line em 3 de Março, 2013, DOI: http://dx.doi.org/10.1007/s10836-013-5358-z.
63- J. Semiao, J. Pachito, C. Martins, B. Jacinto, J. Vazquez, V. Champac, M. Santos, I. Teixeira, J. Teixeira, "Aging-aware Power or Frequency Tuning with Predictive Fault Detection", IEEE Design & Test of Computers, Volume 29 , Issue 5, September/October 2012, DOI: http://dx.doi.org/10.1109/MDT.2012.2206009.
62- J. Semiao, J. Pachito, C. Martins, M. Santos, I. Teixeira, P. Teixeira, “The Influence of Clock-Gating On NBTI-Induced Delay Degradation”, 18th IEEE International On-Line Testing Symposium – IOLTS’12, Sitges, Spain, June 27-29, 2012, DOI: http://dx.doi.org/10.1109/IOLTS.2012.6313842.
61- J.Freijedo, J.Semião, J.J.Rodríguez Andina, F.Vargas, I.C.Teixeira, J.P.Teixeira, “Modeling the effect of process, power-supply voltage and temperature variations on the timing response of nanometer digital circuits”, Journal of Electronic Testing: Theory and Applications (JETTA), Online First™, 1 May 2012, DOI: http://dx.doi.org/10.1007/s10836-012-5297-0.
60- R.S. Oliveira, J. Semião, I.C. Teixeira, M.B. Santos, J.P. Teixeira, "On-Line BIST for Performance Failure Prediction under NBTI-Induced Aging in Safety-Critical Applications ", Journal of Low Power Electronics (JOLPE), Volume 7, Number 4, December 2011, DOI: http://dx.doi.org/10.1166/jolpe.2011.1155.
59- C. Martins, J. Pachito, J. Semião, I. C. Teixeira, J. P. Teixeira, "Adaptive Error-Prediction Aging Sensor for On-Line Monitoring of Performance Errors", Proceedings of the 26th Conference on Design of Circuits and Integrated Systems - DCIS'2011, Albufeira, Portugal, November 16-18, 2011 (link).
58- D.Silva, L.B.Poehls, J.Semião, I.C.Teixeira, J.P.Teixeira, M.Valdés, J.Freijedo, J.J.Rodríguez-Andina, F.Vargas, "IP core to leverage RTOS-based embedded systems reliability to Electromagnetic Interference", EMC Compo 2011 — 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits, Dubrovnik, November 6-9, 2011 (link).
57- V.Bexiga, C.Leong, J.Semião, M.Valdés, J.Freijedo, J.J.Rodríguez-Andina, F.Vargas, I.C.Teixeira, J.P.Teixeira, "Performance failure prediction using built-in delay sensors in FPGAs", FPL'2011 — 21st International Conference on Field Programmable Logic and Applications, Chania, Crete, September 5-7, 2011, DOI: http://dx.doi.org/10.1109/FPL.2011.61.
56- C. V. Martins, J. Semião, J. C. Vazquez, V. Champaq, M. Santos, I. C. Teixeira, J. P. Teixeira, "Adaptive Error-Prediction Flip-flop for Performance Failure Prediction with Aging Sensors", 29th IEEE VLSI Test Symposium 2011 (VTS'11), Dana Point, California, USA, May 1st - 5th, 2011, DOI: http://dx.doi.org/10.1109/VTS.2011.5783784.
55- J. Freijedo, M. D. Valdés, L. Costas, M. J. Moure, J. J. Rodríguez-Andina, J. Semião, F. Vargas, I. C. Teixeira, J. P. Teixeira, "Lower VDD Operation of FPGA-Based Digital Circuits through Delay Modeling and Time Borrowing", Journal of Low Power Electronics (JOLPE), Volume 7, Number 2, April 2011 , American Scientific Publishers, DOI: http://dx.doi.org/10.1166/jolpe.2011.1127.
54- Ricardo Oliveira, Jorge Semião, Isabel Teixeira, Marcelino Bicho dos Santos, Paulo Teixeira, "On-line BIST for Performance Failure Prediction under Aging Effects in Automotive Safety-Critical Applications", LATW'11 - 12th IEEE Latin-American Test Workshop, Porto de Galinhas, Brazil, March 27th-30th, 2011, DOI: http://dx.doi.org/10.1109/LATW.2011.5985919.
53- Judit Freijedo, Jorge Semião, Juan J. Rodriguez-Andina, Fabian Vargas, Isabel Teixeira, Paulo Teixeira, "Modeling the effect of process variations on the timing response of nanometer digital circuits", LATW'11 - 12th IEEE Latin-American Test Workshop, Porto de Galinhas, Brazil, March 27th-30th, 2011, DOI: http://dx.doi.org/10.1109/LATW.2011.5985927.
52- M. Valdés, J. Freijedo, M. J. Moure, J. J. Rodríguez-Andina, J. Semião, F. Vargas, I.C. Teixeira, J.P. Teixeira, "Programmable Sensor for On-Line Checking of Signal Integrity in FPGA-Based Systems Subject to Aging Effects", LATW'11 - 12th IEEE Latin-American Test Workshop, Porto de Galinhas, Brazil, March 27th-30th, 2011, DOI: http://dx.doi.org/10.1109/LATW.2011.5985926.
51- F. Lavratti, L. Bolzani, J.Semião, F.Vargas, I.C.Teixeira, J.J.Rodríguez-Andina, J.P.Teixeira, "Clock signal modulation for IC electromagnetic compatibility", WRTLT'2010 — IEEE Eleventh Workshop on RTL and High Level Testing, Shanghai, December 5-6, 2010.
50- F. Lavratti, L. Bolzani, J.Semião, F.Vargas, I.C.Teixeira, J.J.Rodríguez-Andina, J.P.Teixeira, "Clock signal modulation for IC electromagnetic compatibility", WRTLT'2010 — Journal of Shangai Normal University, October, 2010, DOI: http://dx.doi.org/10.3969%2fj.issn.1000-5137.2010.05.003.
49- J.Freijedo, M.D.Valdés, M.J.Moure, L.Costas, J.J.Rodríguez-Andina, J.Semião, F.Vargas, I.C.Teixeira, J.P.Teixeira, "Aplicación de modelos de variación de retardo al incremento de robustez ante variaciones de tensión de alimentación en FPGAs", JCRA 2010 — X Jornadas de Computación Reconfigurable y Aplicaciones, Valencia, September 7-10, 2010.
48- J.Freijedo, L. Costas, J.Semião, J.J.Rodríguez-Andina, M.J.Moure, F.Vargas, I.C.Teixeira, J.P.Teixeira, "Impact of power supply voltage variations on FPGA-based digital systems performance", Journal of Low Power Electronics (JOLPE), Volume 6, Number 2, August 2010 , pp. 339-349(11), American Scientific Publishers, DOI: http://dx.doi.org/10.1166/jolpe.2010.1076.
47- J. Semião, "Metodologias Baseadas na Tensão de Alimentação e Temperatura para Melhorar a Tolerância e a Detecção de Faltas Dinâmicas em Sistemas Integrados Digitais", Dissertação para obtenção do grau de Doutor em Engenharia Electrotécnica e de Computadores, IST, UTL, Julho de 2010 (download).
46- J.Vazquez, V.Champac, A.Ziesemer Jr., R.Reis, J.Semiao, I.Teixeira, M.Santos, J.P.Teixeira, "Predictive Error Detection by On-line Aging Monitoring", IOLTS 2010 — 16th IEEE International On-Line Testing Symposium, Corfu, July 5-7, 2010, http://dx.doi.org/10.1109/IOLTS.2010.5560241.
45- R.Chipana, L.Bolzani, F.Vargas, J.Semião, J.J.Rodríguez-Andina, I.C.Teixeira, J.P.Teixeira, "Investigating the use of BICS to detect resistive-open defects in SRAMs", IOLTS 2010 — 16th IEEE International On-Line Testing Symposium, Corfu, July 5-7, 2010, DOI: http://dx.doi.org/10.1109/IOLTS.2010.5560207.
44- J.Freijedo, M.D.Valdés, M.J.Moure, L.Costas, J.J.Rodríguez-Andina, J.Semião, F.Vargas, I.C.Teixeira, J.P.Teixeira, "Use of time borrowing for lower VDD operation of FPGA-based digital circuits", LPonTR'10 — 3rdInternational Workshop on impact of Low-Power design on Test and Reliability, Prague, May 27-28, 2010 (link).
43- J.Freijedo, M.D.Valdés, M.J.Moure, L.Costas, J.J.Rodríguez-Andina, J.Semião, F.Vargas, I.C.Teixeira, J.P.Teixeira, "Delay modeling for power noise-aware design in Spartan-3A FPGAs", SPL 2010 — VI Southern Programmable Logic Conference, Ipojuca, Porto de Galinhas, March 24-26, 2010, DOI: http://dx.doi.org/10.1109/SPL.2010.5483026.
42- Jorge Semião, Judit Freijedo, Fabian Vargas, Marcelino Santos, Isabel Teixeira, Juan Jose Rodriguez-Andina, João Paulo Teixeira, “Comparing the Efficiency of a Clock-Signal Modulation Technique for System-on-Chip in Conducted Versus Radiated EMI Environments”, EMC Compo 09, Toulouse, November 2009.
41- J.Semiao, J.Freijedo, J.J. Rodriguez-Andina, F.Vargas, M.Santos, I.Teixeira, J.P.Teixeira, “Delay-Fault Tolerance to Power Supply Voltage Disturbances Analysis in Nanometer Technologies”, Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS’09), held in Sesimbra, Portugal, June 24-26, 2009, pp. 223-228, ISBN 978-1-4244-4822-7, DOI: http://dx.doi.org/10.1109/IOLTS.2009.5196020.
40- J. Freijedo, L.Costas, J. Semião, J.J. Rodríguez-Andina, M.J.Moure, F.Vargas, I.C.Teixeira, J.P.Teixeira, “Delay Modeling for Power Noise-Aware Design and Test in 65nm FPGAs”, 2nd International Workshop on Impact of Low-Power design on Test and Reliability (LPonTR'09) Held in Conjunction with the 14th IEEE European Test Symposium 2009, Seville, Spain, May 29th, 2009 (link).
39- Jorge Semião, “Power-Supply and Temperature Based Methodologies to Improve Tolerance and Detection of Delay Faults in Synchronous Digital Circuits”, oral and poster presentation in the students forum at the 14th IEEE European Test Symposium (ETS), Sevilla, Spain, May 25-29, 2009.
38- Jorge Semião, Judite Freijedo, Marlon Moraes, Marcelo Mallmann, Cláudia Antunes, Juliano Benfica, Fabian Vargas, Marcelino Santos, Isabel C. Teixeira, Juan-Jose Rodríguez Andina, João Paulo Teixeira, Daniel Lupi, Edmundo Gatti, Luís Garcia, Fernando Hernandez, “Measuring Clock - Signal Modulation Efficiency for Systems - on - Chip in Electromagnetic Interference Environment”, LATW’09 - 10th Latin-American Test Workshop, Búzios, Rio de Janeiro, Brazil, March 2-5, 2009, DOI: http://dx.doi.org/10.1109/LATW.2009.4813817.
37- J. Freijedo, J. Semião, J. Rodriguez-Andina, F. Vargas, I.C. Teixeira, J.P. Teixeira, “Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems”, Journal of Low Power Electronics, Special Issue on LPonTR, Vol. 4 N° 3 December 2008. DOI: http://dx.doi.org/10.1166/jolpe.2008.191
36- J. Semião, J. Freijedo, J. Rodriguez-Andina, F. Vargas, M.B. Santos, I.C. Teixeira, J.P. Teixeira, “Time Management for Low-Power Design of Digital Systems”, Journal of Low Power Electronics, Special Issue on LPonTR, Vol. 4 N° 3 December 2008. DOI: http://dx.doi.org/10.1166/jolpe.2008.194
35- J. Semião, J. Varela, J. Freijedo, J. Rodriguez-Andina, C. Leong, P. Teixeira, I. Teixeira, “Robust Solution for Synchronous Communication among Multi Clock Domains”, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2008), Nov. 30 2008-Dec. 3 2008, page(s): 1107-1110, E-ISBN: 978-1-4244-2342-2, ISBN: 978-1-4244-2341-5, DOI: http://dx.doi.org/10.1109/APCCAS.2008.4746218.
34- J. Semião, M. Rodriguez-Irago, L. Piccoli, F. Vargas, M. B. Santos, I. C. Teixeira, J. J. Rodríguez-Andina, J. P. Teixeira, “Signal Integrity Enhancement in Digital Circuits”, IEEE Design and Test of Computers, September-October 2008, vol. 25, no. 5, pp. 452-461, ISSN: 0740-7475. http://doi.ieeecomputersociety.org/10.1109/MDT.2008.146
33- J. Semião, J. Freijedo, M. Moraes, M. Mallmann, C. Antunes, J. Benfica, F. Vargas, M. Santos, I. C. Teixeira, J. J. Rodríguez Andina, J. P. Teixeira, D. Lupi, E. Gatti, L. Garcia, F. Hernandez, “Power-Supply Instability Aware Clock Signal Modulation for Digital Integrated Circuits”, EMC Europe 2008 - International Symposium on Electromagnetic Compatibility (EMC), Hamburg, Germany, September 8-12, 2008, pages: 1-6, ISBN: 978-1-4244-2737-6, DOI: http://dx.doi.org/10.1109/EMCEUROPE.2008.4786876.
32- J.Semião, J.Freijedo, J.J.Rodríguez Andina, F.Vargas, M.B.Santos, I.C.Teixeira, J.P.Teixeira, “Exploiting parametric power supply and/or temperature variations to improve fault tolerance in digital circuits”, IOLTS 2008 - 14th IEEE International On-Line Testing Symposium, Rhodes, July 7-9, 2008, DOI: http://dx.doi.org/10.1109/IOLTS.2008.51.
31- J. Freijedo, J. Semião, J.J. Rodríguez-Andina, F.Vargas, I.C.Teixeira, J.P.Teixeira, “Delay Modeling for Power Noise-Aware Design and Test of Nanometer Digital Circuits”, Workshop on Low Power Design Impact on Test and Reliability (LPonTR) (In Conjunction with IEEE European Test Symposium 2008), Pallanza, Lago Maggiore, Italy, May 29, 2008 (link).
30- J. Semião J. Freijedo, J. Andina F. Vargas M. Santos, I. Teixeira, P. Teixeira, “Power and Time Management for Low-Power Design”, Workshop on Low Power Design Impact on Test and Reliability (LPonTR) (In Conjunction with IEEE European Test Symposium 2008), Pallanza, Lago Maggiore, Italy, May 29, 2008 (link).
29- J.Semião, J.J.Rodríguez-Andina, F.Vargas, M.B.Santos, I.C.Teixeira, J.P.Teixeira, “Process tolerant design using thermal and power-supply tolerance in pipeline based circuits”, DDECS 2008 - 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Bratislava, April 16-18, 2008, DOI: http://dx.doi.org/10.1109/DDECS.2008.4538752.
28- J.Freijedo, J.Semião, J.J.Rodríguez-Andina, F.Vargas, I.C.Teixeira, J.P.Teixeira, “An accurate path delay model for multi-VDD dynamic testing of digital circuits”, LATW 2008 - 9th IEEE Latin American Test Workshop, Puebla, February 17-20, 2008.
27- J.Semião, J.J.Rodríguez-Andina, F.Vargas, M.B.Santos, I.C.Teixeira, J.P.Teixeira, “A fault-tolerant methodology to design power and thermal noise-aware pipeline architectures”, LATW 2008 - 9th IEEE Latin American Test Workshop, Puebla, February 17-20, 2008 (link).
26- F. Vargas, J. Benfica, M. Moraes, E. Gatti, L. Garcia, D. Lupi, F. Hernandez, J. Semião, J. Freijedo, M. B. Santos, I. C. Teixeira, J. J. Rodríguez Andina, J. P. Teixeira, “SoC Prototyping Environment for EMC-Dependability Measurements”, DECIDE 2007 – Fisrt International Workshop on Dependable Circuit Design, Buenos Aires, Argentina, December 6 – 7, 2007 (link).
25- J. Semião, J. Freijedo, M. Moraes, F. Vargas, M. B. Santos, I. C. Teixeira, J. J. Rodríguez Andina, J. P. Teixeira, “System-on-Chip Signal Integrity Enhancement Based on Dynamic Clock Management”, Proceedings of the 6th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2007), Torino, Italy, November 28th - 30th, 2007 (link).
24- J. Semião, J. J. Rodriguez-Andina, F. Vargas, M. B. Santos, I. Teixeira, J. P. Teixeira, “Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations”, Proceedings of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), pages 303-311, ISBN: 0-7695-2885-6, ISSN: 1550-5774, Rome, Italy, September 26-28, 2007, DOI: http://dx.doi.org/10.1109/DFT.2007.60.
23- J. Semião, J. Freijedo, J. J. Rodríguez-Andina, F. Vargas, M. B. Santos, I. C. Teixeira and J. P. Teixeira, “On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits”, Proceedings of the 13th International Online Testing Symposium (IOLTS’07), Crete, Greece, July 9-11, 2007, DOI: http://dx.doi.org/10.1109/IOLTS.2007.49
22- J. Semião, J. Freijedo, J. Rodríguez-Andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira, “Mixed-signal Design of Dynamic Delay Buffers to Improve Tolerance to Power Supply and Temperature Variations”, Proceedings of the 13th International Mixed Signals Testing Workshop 2007 (IMSTW’07), p2.2, pages 130-135, ISBN: 978-972-99181-2-4, Póvoa de Varzim, Portugal, June 18-20, 2007 (link)
21- J. Semião, J. Freijedo, J. Rodriguez-Andina, F. Vargas, M. Santos, I. Teixeira, J. Teixeira, “Enhancing the Tolerance to Power-Supply Instability in Digital Circuits”, Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2007 (ISVLSI’07), Porto Alegre, Brazil, Maio 9-11, 2007, DOI: http://dx.doi.org/10.1109/ISVLSI.2007.44.
20- J. Semião, J. Freijedo, J. Rodríguez−Andina, F. Vargas, M. Santos, I. Teixeira, J. Teixeira, “Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits”, Proceedings of the 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), pp. 295-300, ISBN: 1-4244-1161-0, Krakow, Poland, April 11-13, 2007, DOI: http://dx.doi.org/10.1109/DDECS.2007.4295299.
19- M. Rodriguez-Irago, J. Rodriguez-Andina, J. Semiao, F. Vargas, I. Teixeira, J. Teixeira, “A Model for the Analytical Definition of Multi-VDD, Multi-T Dynamic Tests in Nanometer Digital Circuits”, Proceedings of the 8th IEEE Latin-American Test Workshop (LATW’07), Cuzco, Peru, March 11 - 14, 2007 (link).
18- J. Semião, M. Rodriguez-Irago, M. Santos, J. Teixeira, I. Teixeira, L. Piccoli, F. Vargas, J. Rodriguez-Andina, “Digital Circuit Signal Integrity Enhancement by Monitoring Power Grid Activity”, Proceedings of the 8th IEEE Latin-American Test Workshop (LATW’07), Cuzco, Peru, March 11 - 14, 2007 (link).
17- J. Semião, M. Rodriguez-Irago, J. Rodriguez-Andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira, “Resistive Open and Bridging Defects Detection in Digital Systems Using Multi-VDD Self-test”, Proceedings of the DCIS’06 , ISBN 978-84-690-4144-4, Barcelona, Spain, November 22-24, 2006 (link).
16- M. Rodríguez Irago, J. J. Rodríguez Andina, F. Vargas, J. Semião, I. C. Teixeira, J. P. Teixeira, “Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes”, IOLTS06 – Proceedings of the 12th IEEE International On-Line Testing Symposium, Lake of Como, Italy, July, 2006, DOI: http://dx.doi.org/10.1109/IOLTS.2006.25.
15- M. Rodríguez Irago, J. J. Rodríguez Andina, F. Vargas, J. Semião, I. C. Teixeira, J. P. Teixeira, “On the Use of Multi-Clock, Multi-VDD and Multi-Temperature Schemes to Improve Dynamic Fault Detection in Digital Systems”, Poster accepted at ETS06 – 11th IEEE European Test Symposium, Southapton, United Kingdom, May, 2006.
14- F. Guerreiro, J. Semiao, A. Pierce, M.B. Santos, I. M. Teixeira, J. P. Teixeira, “Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage”, Proceedings of the DDECS’06 – 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Prague, Czech Republic, April, 2006, DOI: http://dx.doi.org/10.1109/DDECS.2006.1649635.
13- Patente Nacional (Portugal) – 103436, com o título “Aumento de Tolerância Dinâmica de Circuitos Electrónicos Integrados Digitais a Variações de Tensão de Alimentação e de Temperatura”, em 17 de Fevereiro de 2006, requerida por INESC-ID, Universidade de Vigo – CACTI e por PUCRS (Pontifícia Universidade Católica do Rio Grande do Sul), pelos inventores: João Paulo Cacho Teixeira; Isabel Cacho Teixeira; Marcelino Bicho dos Santos; Jorge Filipe Leal Costa Semião; Juan Rodriguez Andina, Marcial Irago, Fabian Vargas e Leonardo Piccoli.
12- Hélio Santos, Miguel Silva, Jorge Semião, “Serviço de Vídeo a Pedido Através da Internet”, TecnoVisão – Revista de Divulgação Tecnológica da Escola Superior de Tecnologia da Universidade do Algarve Nº14, pág. 12-14, Janeiro, 2003, Faro - Portugal.
11- O.P. Dias, M. B. Santos, J. Semião, J. P. Teixeira, C.E. Pereira, I.M. Teixeira " Quality Metrics and Criteria for Architectural Design and Test of Hw/Sw Systems. Methodologies and Tools ", Proceedings 5th. World Multi-Conf. On Systemics, Cybernetics and Informatics (SCI), pp., Orlando, Flo., July, 2001
10- J. Semião, "DFT Insertion Techniques at System Level in Hardware/Software (Hw/Sw) Systems", M.Sc. Thesis, IST, TUL, May 2001.
9- O.P. Dias, J. Semião, I.M. Teixeira and J.P. Teixeira, "Test Resource Partitioning: A Design and Test Issue", Proceedings of the Design Automation and Test in Europe (DATE) Conference (Embedded Tutorial - TRP: Integrating Embedded Test and ATE, invited), pp., Munich, March, 2001, DOI: http://dx.doi.org/10.1109/DATE.2001.914997.
8- O.P. Dias, J. Semião, I.M. Teixeira and J.P. Teixeira, "TRP Quality Assessment: Trade-off Analysis", 1st. IEEE International Workshop on Test Resource Partitioning (TRP) Informal Digest, pp. 2.2-1-8, October, 2000, Atlantic City, DOI: http://dx.doi.org/10.1109/DATE.2001.914997.
7- O.P. Dias, J. Semião, M.B. Santos, I.M. Teixeira, J.P. Teixeira, C.E. Pereira, “MOSYS: A Methodology for Automatic Object Identification from System Specification”, Proceedings of the 3rd. IEEE International Symposium on Object-Oriented Real Time Distributed Computing (ISORC), March, 2000, Newport Beach, California.
6- O. P. Dias, J. Semião, M. B. Santos, I. M. Teixeira and J. P. Teixeira, “Quality of Electronic Design: from Architectural Level to Test Coverage”, Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED), pp.197-202, March, 2000, San Jose, California, DOI: http://dx.doi.org/10.1109/ISQED.2000.838874.
5- O. P. Dias, J. Semião, I. M. Teixeira, J. P. Teixeira, C. E. Pereira, “Introducing Test Requirements in Real-Time Systems at Architectural Level”, Proceedings of the 14th Conference on Design of Circuits and Integrated Systems (DCIS), pp. 289-294, November, 1999, Palma de Mallorca, Spain.
4- O. P. Dias, J. Semião, C. E. Pereira I. M. Teixeira, J. P. Teixeira, “Hardware/Software Specification, Design and Test Using a System Level Approach”, Proceedings of the Symposium on Integrated Circuits and Systems Design (SBCCI), pp. 42-45, October, 1999, Brazil, DOI: http://doi.ieeecomputersociety.org/10.1109/SBCCI.1999.802964.
3- O. P. Dias J. Semião, M. B. Santos, I. M. Teixeira C. E. Pereira and J. C. Teixeira, “Desenvolvimento de Arquitecturas Testáveis em Sistema Físicos e Lógicos (Hardware/Software)”, 4º Encontro da Engenharia Electrotécnica, número especial dos Anais da Engenharia Electrotécnica, pp. 111-117, Maio, 1999, Lisboa - Portugal.
2- O. P. Dias J. Semião, M. B. Santos, I. C. Teixeira and J. C. Teixeira, “From System Level to Defect-Oriented Test: a Case Study”, Proceedings of the European Test Workshop, (ETW’99), pp. 136-141, May, 1999, Konstanz - Germany, DOI: http://dx.doi.org/10.1109/ETW.1999.804509.
1- O. P. Dias, J. Semião, I. M. Teixeira and J. P. Teixeira, “Soft Rapper Design for Embedded Cores Using a System Level Approach” Digest of 3rd. IEEE International Workshop on Testing Embedded Core-Based System-Chips (TECS), pp. 4.4.1-7, April, 1999, Dana Point, California.

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